1) Field of the Invention
The present invention relates to an art for creating a library which is used in operation verification of circuitry designed in a hierarchical form.
2) Description of the Related Art
A method of hierarchical design has often been employed at design of large-scale circuitry. In hierarchical design, upper-level large-scale circuitry is divided into multiple lower-level small-scale circuits. After design and operation verification (hereafter, also simply called verification) are performed for each of the small scale circuits, the small scale circuits, having already been designed, are combined, and then design and verification is performed for the upper-level large-scale circuitry.
Here, the number of hierarchical levels used in hierarchical design is not limited to two, the upper level and the lower level, and three or more hierarchical levels can be employed in design.
At verification of hierarchically designed circuitry, some lower-level circuits (regions) are sufficient to be verified by themselves. Some other lower-level circuits need to be combined before verification as upper-level circuits, and some other lower-level circuits need to be combined with upper-level circuits to be verified.
When an upper-level circuit is verified, libraries are firstly created, one for each of the multiple lower-level circuits, and generally speaking, such libraries are then combined to perform operation verification of the upper-level circuit. Here, a library means a table, etc., recording therein characteristic values of a circuit. Such a library is realized by storing characteristic values of each circuit in a recording medium, such as a memory or a hard disk, in association with the circuits.
Preparing such libraries of lower-level circuits makes it possible to efficiently perform verification of upper-level circuits, and the time required for verification is reduced.
In such a case, the libraries of lower-level circuits must include information sufficient to perform verification of the upper-level circuits.
Here, as an example of verification of circuitry, a description will be made of delay verification among FFs (Flip-Flops) 101a through 101f of asynchronous circuit 100 of FIG. 10. That is, as shown in FIG. 11, a description will be made of delay verification between FFs in order to evaluate whether or not a signal can travel from a certain FF to the next FF in the downstream direction (the direction in which the signal proceeds) during one cycle time (for example, 1 sec/frequency).
As shown in FIG. 10, the synchronous circuit 100 includes multiple (here, six) FFs 101a through 101f. In this example, circuitry (indicated by the one-dotted line in FIG. 10) ranging from the terminal 104 to the terminal 105, which circuitry includes FFs 101c through 101e, is given as a lower-level circuit 102. The other parts of the synchronous circuit 100 than the lower-level circuit 102 thereof are given as upper-level circuits 103.
Like this synchronous circuit 100, hierarchical design would sometimes result in multiple FFs 101c through 101e present in a lower-level circuit 102.
In this case, as shown in FIG. 12, delay verification among multiple FFs 101c through 101e, that is, between the FF 101c and the FF 101d and between the FF 101d and the FF 101e, can be carried out in the lower level circuit 102.
That is, if there are is an FF for sending a signal and an FF for receiving the signal within the lower-level circuit 102, delay verification between these two FFs can be performed within the lower-level circuit 102.
In contrast, in the synchronous circuit 100, delay verification of a region between FFs whose hierarchical level is separated by the lower-level circuit 102, that is, a region between the FF 101b and the FF 101c and a region between the FF 101e and the FF 101f, cannot be performed within the lower-level circuit 102. Thus, the lower-level circuit 162 should be combined with the upper level circuit 103 for verification.
Accordingly, in the lower-level circuit 102, as to a part upstream of the FF 101c where an upstream FF 101b for sending out a signal is not present, that is, a part ranging from the terminal 104, which is the input end (upstream end) of the lower-level circuit 102, to the FF 101c, a library of delay (characteristic value) of this part is created. In addition, in the upper-level circuit 103, as to a part between the FF 101b and the terminal 104, which is the output terminal thereof, a library of delay of this part is created. Then, these libraries are combined and verified, delay verification between the FF 101b and the FF 101c being thereby performed.
Likewise, in the lower-level circuit 102, as to a part downstream of the FF 101e where a downstream FF 101f for receiving a signal is not present, that is, a part ranging from the terminal 105, which is the output end (downstream end) of the lower-level circuit 102, to the FF 101e, a library of delay (characteristic values) of this part is created. In addition, in the upper-level circuit 103, as to a part between the FF 101f and the terminal 105, which is the input terminal thereof, a library of delay of this part is created. Then, these libraries are combined and verified, delay verification between the FF 101e and the FF 101f being thereby performed.
Next, taking an example of the circuit 110 with a construction shown in FIG. 13, a description will be made hereinbelow of a simulation method (library creating method) used when timing analysis (delay verification) of the whole of the circuit 110 is performed. It is to be noted that this simulation method is also used in delay verification of the lower-level circuit 102 of FIG. 10 having already been described.
In the beginning, a description will be made of the circuit 110 of FIG. 13. The circuit 110 includes a RAM (Random Access Memory), FFs (latches), and combinational logics (combinational circuits), and each of these is formed by a combination of transistors.
When timing analysis of the whole of the circuit 110 is performed, a collective simulation of the whole of the circuit 110 will not be executed. As shown in the flowchart (step S100 through step S105) of FIG. 14, an analysis object circuit 110 is divided into simulation unit circuits, and delay characteristics are measured for each simulation unit circuit, and the measured characteristics are summed up (statistic timing analysis).
More specifically, a designer inputs and selects a simulation object circuit 110 (step S100), and when a simulator for executing simulation acknowledges the circuit 110 (step S101), the simulator divides the circuit 110 into multiple simulation unit regions (simulation unit circuits) 110a through 110e as shown in FIG. 15 (step S102).
This dividing process (the above step S102) of the simulation unit regions 110a through 110e is carried out by separating the circuit 110 at points appropriate for separation (for example, the number of transistors, the operation content of circuits, or timing characteristics).
Then, the simulator performs simulation for each simulation unit region, which has been obtained as a result of separation (step S103), and characteristics for each simulation unit region are obtained (step S104).
This simulation process (the above step S103) uses a simulator [represented by a SPICE (Simulation Program with Integrated Circuit Emphasis)] to perform operation simulation, thereby measuring characteristics, such as delay, of each of the simulation unit regions.
After that, the simulator totalizes the characteristics of each of the simulation unit regions obtained by the simulation process (step S104), and the totalized characteristics are recorded and stored in a memory, a library being thereby created (step S105). The processing then ends.
In cases where a desired path whose library is to be created is composed of multiple simulation unit regions, the totalizing process (the above step S104) of characteristics of each simulation unit region is realized by totalizing the characteristics of the multiple simulation unit regions. As the simplest totalizing method, the characteristics of the multiple simulation unit regions are summed up, whereby the totalizing process is carried out.
Taking an example where the characteristic obtained as a result of the simulation process is a delay time, when a library of delay of a desired path is to be created, delay times as the characteristics of the multiple simulation unit regions forming the path are summed up, whereby a delay time of the desired path is obtained.
More concretely, when applying the above technique to the lower-level circuit 102 of FIG. 10, the totalizing process of the characteristic recognizes a region from the FF 101c to the FF 101d and a region from the FF 101d to the FF 101e as separate paths whose libraries are to be created. As a result of the totalizing process, the characteristic value of these paths is calculated.
In this instance, various methods for simulating logic circuits have been proposed (for example the following patent document 1).
Here, when hierarchical design is carried out as described above with reference to FIG. 10, the lower-level circuit 102 includes circuitry (region) whose verification must be performed with the lower-level circuit 102 and the upper-level circuit 103 combined with each other, and also circuitry (region) whose verification can be performed within the lower-level circuit 102.
More specifically, a region from the input end (terminal 104) of the lower-level circuit 102 to the FF 101c and a region from the output end (terminal 105) to the FF 101e must be combined with the upper-level circuit 103 at the time of verification. In contrast, a region from the FF 101c to the FF 101d and a region from the FF 101d to the FF 101e can be verified within the lower-level circuit 102.
However, in the previous art, when the lower-level circuit 102 and the upper-level circuit 103 are combined for verification of the synchronous circuit 100, verification of the whole of the lower-level circuit 102 is performed once again, and a library is created, taking the whole of the lower-level circuit 102 as an object.
Therefore, verification and library creation are carried out for a region from the FF 101c to the FF 101d and a region from the FF 101d to the FF 101e, regions for which combination with the upper-level circuit 103 for verification is unnecessary, so time is expended in useless processing.
Moreover, such circuitry, whose library need not be created, is also divided into simulation unit regions with the simulation technique (library creating method) shown in FIG. 14, and the thus-obtained multiple simulation unit regions are simulated, so that a long time is expended in the simulation processing. Further, since the process of totalizing characteristics obtained as a result of simulation of the multiple simulation unit regions is also necessary, the process time for creating a library is greatly increased.
[Patent Document] Japanese Patent Application Laid-open No. HEI 10-149385